My research interests lie on the design, fabrication and characterization of novel optoelectronic devices that are utilized III-V, Si or 2D materials. My research interests also span to slow-light photonics, high-contrast gratings for metastructure waveguide and nano photonic arrays for meta surface applications, and on-chip lightwave circuit integration for optical interconnects, RF photonics and optical neuromorphic computing applications.
I am also seeking dedicated graduate students who have background in photonics, optics, optoelectronics or solid-state physics to join my research group. If interested, you may contact me at email@example.com with subject title of “graduate student candidate”.
The details of areas I am currently are working on are listed below:
True time optical delay line is an essential component for many optical systems as well as for on-chip lightwave circuits. For bench top demonstrations, a fiber spool with several kilometers is often used to produce the needed delay time. As the field is making paradigm shift from system-on-a-bench to system-on-a-chip, integrated on-chip true time optical delay line become a critical photonic device. It is challenging to achieve integrated waveguides that has low loss as optical fibers with foot print adequately small to fit into on-chip integration. My group uses the approach of Si/SiO2 and SiN/SiO2 cascade apodized slow-light transmission grating waveguide to produce true time delay lines. The measured group index of a slow-light Bragg grating in our group has reached ng ~ 17, i.e. light is slowed down for a factor of ~ 17 in comparison to speed of light in free space.
As to further increase the group index, metastructure waveguide has been explored. It uses drastically different wave confining mechanism that involves the leaking wave resonance. Using this method, we aim to obtain a waveguide that offers group index ng > 100.
High-speed photodetectors and modulators are basic building blocks for on-chip optical communication network. In my group, I am particularly interested in planar metal-semiconductor-metal waveguide photodetectors for optical interconnect applications. For the Si modulator research, we focus on SiGe heterojunction bipolar transistor (HBT) type of three-terminal majority carrier injection type of modulator as it offers both high modulation efficiency (Vπ⋅Lπ = 0.00011cm-V) and high operation speed (>80GHz).
High performance, low cost and small footprint large array Si modulators are in high demand for many RF photonics systems in which discrete LiNBO3 modulators are too bulky and expensive to implement. In my research group, we focus on low-voltage foundry based Si modulators that offer small footprint, and large spur-free dynamic range (SFDR).
Phased array antennas (PAAs) have been widely used in both military platform and commercial radio-frequency (RF) systems. Tunable true-time delays (TTD) is one scheme in beamforming for optically controlled phased array antennas. In collaborating with Army Research Lab, we are exploring a simple beamforming architecture that offers two-dimensional spatial scanning of the antenna radiation field. The key element is an on-chip integrated Si slow-light grating waveguide that exhibits wavelength-dependent group velocity.
Brain inspired artificial neural network (ANN) is a promising approach in processing highly complex or abstract computational tasks. Neuromorphic computing based on integrated CMOS circuits have been extensively studied and successfully commercialized. Lately, research has shown that optical reservoir computing will offer several orders of magnitude of power reduction as well as increased computation speed compared to electrical neuromorphic computing chips. In my group, we adopt true-time delay line reservoir approach for analog optical computing. The signals are processed in optical domain, and stored and distributed temporally in a reservoir, i.e. the optical delay line to provide short term memory. The true time delay line RC network offers the advantage of much reduced complexity in hardware implementation. This work is in collaboration with AFRL at Rome.