Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 pass_S~2.asm Page 1 1 ;*************************************************************************** 2 ;QS_ST.ASM : WILL PASS AUDIO STRAIGHT THROUGH 3 ;*************************************************************************** 1067 1068 ;****************************************************************************** 1069 1070 ;---Buffer for talking to the CS4215 1071 1072 X:000000 org x:0 1073 RX_BUFF_BASE 1074 000000 equ * 1075 RX_data_1_2 1076 X:000000 ds 1 ;data time slot 1/2 for RX ISR 1077 RX_data_3_4 1078 X:000001 ds 1 ;data time slot 3/4 for RX ISR 1079 RX_data_5_6 1080 X:000002 ds 1 ;data time slot 5/6 for RX ISR 1081 RX_data_7_8 1082 X:000003 ds 1 ;data time slot 7/8 for RX ISR 1083 1084 TX_BUFF_BASE 1085 000004 equ * 1086 TX_data_1_2 1087 X:000004 ds 1 ;data time slot 1/2 for TX ISR 1088 TX_data_3_4 1089 X:000005 ds 1 ;data time slot 3/4 for TX ISR 1090 TX_data_5_6 1091 X:000006 ds 1 ;data time slot 5/6 for TX ISR 1092 TX_data_7_8 1093 X:000007 ds 1 ;data time slot 7/8 for TX ISR 1094 1095 X:000008 RX_PTR ds 1 ; Pointer for rx buffer 1096 X:000009 TX_PTR ds 1 ; Pointer for tx buffer 1097 1098 ;TONE_OUTPUT EQU HEADPHONE_EN+LINEOUT_EN+(4*LEFT_ATTN)+(4*RIGHT_ATTN) 1099 ;TONE_INPUT EQU MIC_IN_SELECT+(15*MONITOR_ATTN) 1100 ;CTRL_WD_12 equ NO_PREAMP+HI_PASS_FILT+SAMP_RATE_48+STEREO+DATA_16 ;CLB=0 1101 ;CTRL_WD_34 equ IMMED_3STATE+XTAL1_SELECT+BITS_64+CODEC_MASTER 1102 ;CTRL_WD_56 equ $000000 1103 ;CTRL_WD_78 equ $000000 1104 1105 000300 CTRL_WD_12 equ MIN_LEFT_ATTN+MIN_RIGHT_ATTN+LIN2+RIN2 1106 000000 CTRL_WD_34 equ MIN_LEFT_GAIN+MIN_RIGHT_GAIN 1107 1108 1109 P:000050 org p:$50 ;SCI Recieve Data Interrupt 1110 P:000050 0BF080 jsr ISCIRD 00015B 1111 1112 P:000100 org p:$100 1113 START 1114 main 1115 P:000100 08F4BD movep #$040003,x:M_PCTL ; set PLL for MPY of 4X 040003 1116 P:000102 08F4BB movep #$012421,x:M_BCR ; set up one ext. wait state for all AAR areas 012421 Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 pass_S~2.asm Page 2 1117 P:000104 0003F8 ori #3,mr ;mask interrupts 1118 P:000105 0500BB movec #0,sp ;clear hardware stack pointer 1119 P:000106 0500BA move #0,omr ;operating mode 0 1120 P:000107 364000 move #$40,r6 ; initialise stack pointer 1121 P:000108 05F426 move #-1,m6 ; linear addressing FFFFFF 1122 P:00010A 0BF080 jsr ada_init ; initialize codec 000169 1123 1124 1125 ; initialize SCI 1126 ; 10-bit asynchronous mode 1127 ; enable reciever and transmitter 1128 P:00010C 07F41C movep #$000B02,x:M_SCR ; SCI control register 000B02 1129 ; set interrupt priority for SCI RECV to 1 1130 P:00010E 56F000 move x:M_IPRP,a FFFFFE 1131 ; enable tx and rx pins 1132 P:000110 07F41F movep #$000003,x:M_PCRE ; Port E Control Register 000003 1133 P:000112 0140C2 or #000080,a 000050 1134 ; Reciever/Transmitter clocks use external clock from SCLK 1135 P:000114 07F41B movep #$00C000,x:M_SCCR ; SCI Clock Control Register 00C000 1136 P:000116 567000 move a,x:M_IPRP ; interrupt priority peripheral FFFFFE 1137 1138 ;print some random stuff 1139 P:000118 65F400 move #text,r5 000003 1140 P:00011A 0BF080 jsr print 000137 1141 P:00011C 65F400 move #text2,r5 00000C 1142 P:00011E 0BF080 jsr print 000137 1143 1144 ; move #$123456,a1 1145 ; move #$789abc,a0 1146 ; move a,y0 1147 ; debug 1148 1149 1150 loop_1 1151 1152 P:000120 01B7A2 jset #2,x:M_SSISR0,* ;wait for frame sync to pass 000120 1153 P:000122 01B782 jclr #2,x:M_SSISR0,* ;wait for frame sync 000122 1154 1155 P:000124 568000 move x:RX_BUFF_BASE,a ;receive left 1156 P:000125 578100 move x:RX_BUFF_BASE+1,b ;receive right 1157 P:000126 0BF080 jsr process_stereo 000131 Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 pass_S~2.asm Page 3 1158 P:000128 560400 move a,x:TX_BUFF_BASE ;transmit left 1159 P:000129 570500 move b,x:TX_BUFF_BASE+1 ;transmit right 1160 1161 P:00012A 46F400 move #CTRL_WD_12,y0 ;set up control words 000300 1162 P:00012C 460600 move y0,x:TX_BUFF_BASE+2 1163 P:00012D 46F400 move #CTRL_WD_12,y0 000300 1164 P:00012F 460700 move y0,x:TX_BUFF_BASE+3 1165 1166 P:000130 0C0120 jmp loop_1 1167 1168 process_stereo 1169 P:000131 4EF000 move y:mask,y0 000000 1170 P:000133 200056 and y0,a 1171 P:000134 20005E and y0,b 1172 P:000135 000000 nop 1173 P:000136 00000C rts 1174 1175 1176 ;print subroutine takes address in register r5 1177 ;exits when most significant byte is zero 1178 ;ignores zeros in lower bytes 1179 ; clobbers register y0 1180 print 1181 P:000137 21C600 move a,y0 ; back up reg A 1182 P:000138 5EDD00 prbegin move y:(r5)+,a 1183 P:000139 0140C5 cmp #$00ffff,a ;check to see if done (char=$00) 00FFFF 1184 P:00013B 0D1049 blt prend 00001E 1185 P:00013D 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 00013D 1186 P:00013F 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 00013F 1187 P:000141 567000 move a,x:M_STXH ; send high byte FFFF97 1188 P:000143 0140C6 and #$00ffff,a 00FFFF 1189 P:000145 0140C5 cmp #$0000ff,a 0000FF 1190 P:000147 0597D1 blt prbegin 1191 P:000148 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 000148 1192 P:00014A 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 00014A 1193 P:00014C 567000 move a,x:M_STXM ; send mid byte FFFF96 1194 P:00014E 0140C6 and #$0000ff,a 0000FF 1195 P:000150 014085 cmp #$000000,a 1196 P:000151 0597C7 blt prbegin 1197 P:000152 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 000152 1198 P:000154 019380 jclr #0,x:M_SSR,* ;wait for tx to finish Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 pass_S~2.asm Page 4 000154 1199 P:000156 567000 move a,x:M_STXL ; send low byte FFFF95 1200 P:000158 050FC0 bra prbegin 1201 P:000159 20CE00 prend move y0,a ;restore reg A 1202 P:00015A 00000C rts 1203 1204 1205 P:00015B 56F000 ISCIRD move x:M_SRXH,a FFFF9A 1206 P:00015D 0140C5 cmp #$0d0000,a 0D0000 1207 P:00015F 0D1042 bne isc1 000004 1208 P:000161 56F400 move #$0d0a00,a 0D0A00 1209 P:000163 5E7000 isc1 move a,y:recv 000001 1210 P:000165 65F400 move #recv,r5 000001 1211 P:000167 0D0137 jsr print 1212 1213 P:000168 000004 rti 1214 1215 1216 include 'ada_init.asm' 1217 page 132,60 1218 ;************************************************************************** 1219 ; ADA_INIT.ASM Ver 1.2 1220 ; Example program to initialize the CS4218 1221 ; 1222 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1223 ; Semiconductor Products Sector 1224 ; Wireless Signal Processing Division 1225 ; 1226 ; History: 1227 ; 14 June 1996: RLR/LJD - ver 1.0 1228 ; 21 July 1997: BEA - ver 1.1 1229 ; 23 Sept 1998: TTL - ver 1.2 1230 ;************************************************************************** 1231 X:00000A org x: 1232 1233 ; Codec control constants 1234 X:00000A CTRL_WD_HI ds 1 1235 X:00000B CTRL_WD_LO ds 1 1236 1237 1238 ; GPIO pin constants 1239 1240 ; ESSI0 - audio data GPIO mode 1241 ; DSP CODEC 1242 ; --------------------------- 1243 CODEC_RESET 1244 000000 equ 0 ; bit0 SC00 ---> CODEC_RESET~ 1245 1246 ; ESSI1 - control data GPIO Mode Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 ada_init.asm Page 5 1247 ; DSP CODEC 1248 ;---------------------------- 1249 000000 CCS equ 0 ; bit0 SC10 ---> CCS~ 1250 000001 CCLK equ 1 ; bit1 SC11 ---> CCLK 1251 000002 CDIN equ 2 ; bit2 SC12 ---> CDIN 1252 1253 ;************************************************************************** 1254 ; Initialize the CS4218 codec 1255 ; --------------------------- 1256 ; Serial Mode 4 (SM4), DSP Slave/Codec Master, 32-bits per frame 1257 ; 1258 ; After a reset, the control port must be written once to initialize it 1259 ; if the port will be accessed to read or write control bits. The initial 1260 ; write is a "dummy" write since the data is ignored by the codec. A second 1261 ; write is needed to configure the codec as desired. Then, the control port 1262 ; only needs to be written to when a change is desired, or to obtain status 1263 ; information. 1264 ; 1265 ; Although only 23 bits contain useful data in CDIN, a minimum of 31 bits 1266 ; must be written. 1267 ; 1268 ; CDIN 1269 ;------------------------------------------------ 1270 ; bit 31 0 1271 ;------------------------------------------------ 1272 ; bit 30 mask interrupt 1273 ; 0=no mask on MF5:\INT pin 1274 ; 1=mask on MF5:\INT pin 1275 ;------------------------------------------------ 1276 ; bit 29 DO1 1277 ;------------------------------------------------ 1278 ; bits 28-24 left output D/A sttenuation (1.5dB steps) 1279 ; 00000=No attenuation 0dB 1280 ; 11111=Max attenuation -46.5dB 1281 ;------------------------------------------------ 1282 ; bits 23-19 right output D/A attenuation (1.5dB steps) 1283 ; 00000=No attenuation 0dB 1284 ; 11111=Max attenuation -46.5dB 1285 ;------------------------------------------------ 1286 ; bit 18 mute D/A outputs 1287 ; 0=outputs ON 1288 ; 1=outputs MUTED 1289 ;------------------------------------------------ 1290 ; bit 17 input mux, left select 1291 ; 0=RIN1 1292 ; 1=RIN2 (used on EVM) 1293 ;------------------------------------------------ 1294 ; bit 16 input mux, right select 1295 ; 0=LIN1 1296 ; 1=LIN2 (used on EVM) 1297 ;------------------------------------------------ 1298 ; bits 15-12 left input A/D gain (1.5dB steps) 1299 ; 0000=No gain 0dB 1300 ; 1111=Max gain +22.5dB 1301 ;------------------------------------------------ 1302 ; bits 11-8 right input A/D gain (1.5dB steps) Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 ada_init.asm Page 6 1303 ; 0000=No gain 0dB 1304 ; 1111=Max gain +22.5dB 1305 ;------------------------------------------------ 1306 ; bits 7-0 00000000 1307 ;------------------------------------------------ 1308 ;************************************************************************** 1309 1310 1311 P:000169 org p: 1312 ada_init 1313 1314 ; reset ESSI ports 1315 P:000169 07F43F movep #$0000,x:M_PCRC ; reset ESSI0 port 000000 1316 P:00016B 07F42F movep #$0000,x:M_PCRD ; reset ESSI1 port 000000 1317 1318 ; Set Control Register A and B 1319 P:00016D 07F435 movep #$101807,x:M_CRA0 ; 12.288MHz/16 = 768KHz SCLK 101807 1320 ; prescale modulus = 8 1321 ; frame rate divider = 2 1322 ; 16-bits per word 1323 ; 32-bits per frame 1324 ; 16-bit data aligned to bit 23 1325 1326 P:00016F 07F436 movep #$ff330c,x:M_CRB0 ; Enable REIE,TEIE,RLIE,TLIE, FF330C 1327 ; RIE,TIE,RE,TE0 1328 ; network mode, synchronous, 1329 ; out on rising/in on falling 1330 ; shift MSB first 1331 ; external clock source drives SCK 1332 ; (codec is master) 1333 ; RX frame sync pulses active for 1334 ; 1 bit clock immediately before 1335 ; transfer period 1336 ; positive frame sync polarity 1337 ; frame sync length is 1-bit 1338 1339 ; Configure GPIO pins -- (functionality and direction ) 1340 P:000171 07F43F movep #$0000,x:M_PCRC ; Enable GPIO pin 0 SC00=CODEC_RESET 000000 1341 P:000173 07F42F movep #$0000,x:M_PCRD ; Enable GPIO CSS (pin 0),CCLK (pin 1), CDIN (pin 2) 000000 1342 1343 P:000175 07F43E movep #$0001,x:M_PRRC ; set PC0=CODEC_RESET~ as output 000001 1344 P:000177 07F42E movep #$0007,x:M_PRRD ; set PD0=CCS~ as output 000007 1345 ; set PD1=CCLK as output 1346 ; set PD2=CDIN as output 1347 1348 ; Codec Reset 1349 P:000179 013D00 bclr #CODEC_RESET,x:M_PDRC ; assert CODEC_RESET~ Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 ada_init.asm Page 7 1350 P:00017A 012D00 bclr #CCS,x:M_PDRD ; assert CCS~ -- allows control register to be writte n to 1351 1352 ; Delay to allow Codec to reset 1353 P:00017B 06E883 do #1000,_delay_loop 00017E 1354 P:00017D 06E8A3 rep #1000 ; minimum 50 ms delay 1355 P:00017E 000000 nop 1356 _delay_loop 1357 1358 1359 ; Setting up to send Codec control information 1360 P:00017F 013D20 bset #CODEC_RESET,x:M_PDRC ; deassert CODEC_RESET~ 1361 1362 1363 ; Sending control words 1364 set_control 1365 P:000180 44F400 move #CTRL_WD_12,x0 ; transfer control value to control variable 000300 1366 P:000182 440A00 move x0,x:CTRL_WD_HI 1367 P:000183 240000 move #CTRL_WD_34,x0 1368 P:000184 440B00 move x0,x:CTRL_WD_LO 1369 P:000185 0BF080 jsr codec_control ; send in dummy control information 00018F 1370 P:000187 0BF080 jsr codec_control ; send in correct control information 00018F 1371 1372 1373 ; Set and enable interrupts 1374 P:000189 08F4BE movep #$000c,x:M_IPRP ; set interrupt priority level for ESSI0 to 3 00000C 1375 P:00018B 00FCB8 andi #$fc,mr ; enable interrupts 1376 1377 ; Set ESSI functionality 1378 P:00018C 07F43F movep #$003e,x:M_PCRC ; enable ESSI0 except SC00=CODEC_RESET 00003E 1379 1380 P:00018E 00000C rts 1381 1382 1383 ;------------------------------------------------------------- 1384 ; codec_control routine 1385 ; Input: CTRL_WD_LO and CTRL_WD_HI 1386 ; Output: CDIN 1387 ; Description: Used to send control information to CODEC 1388 ; NOTE: does not preserve the 'a' register. 1389 ;------------------------------------------------------------- 1390 codec_control 1391 P:00018F 200013 clr a 1392 P:000190 012D00 bclr #CCS,x:M_PDRD ; assert CCS 1393 P:000191 548A00 move x:CTRL_WD_HI,a1 ; upper 16 bits of control data 1394 P:000192 0BF080 jsr send_codec ; shift out upper control word 000199 1395 P:000194 548B00 move x:CTRL_WD_LO,a1 ; lower 16 bits of control data 1396 P:000195 0BF080 jsr send_codec ; shift out lower control word 000199 Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 ada_init.asm Page 8 1397 P:000197 012D20 bset #CCS,x:M_PDRD ; deassert CCS 1398 P:000198 00000C rts 1399 1400 1401 ;--------------------------------------------------------------- 1402 ; send_codec routine 1403 ; Input: a1 containing control information 1404 ; Output: sends bits to CDIN 1405 ; Description: Determines bits to send to CDIN 1406 ;--------------------------------------------------------------- 1407 1408 send_codec 1409 P:000199 061080 do #16,end_send_codec ; 16 bits per word 0001A5 1410 P:00019B 012D21 bset #CCLK,x:M_PDRD ; toggle CCLK clock high 1411 P:00019C 0ACC17 jclr #23,a1,bit_low ; test msb 0001A1 1412 P:00019E 012D22 bset #CDIN,x:M_PDRD ; send high into CDIN 1413 P:00019F 0AF080 jmp continue 0001A2 1414 bit_low 1415 P:0001A1 012D02 bclr #CDIN,x:M_PDRD ; send low into CDIN 1416 continue 1417 P:0001A2 0602A0 rep #2 ; delay 1418 P:0001A3 000000 nop 1419 P:0001A4 012D01 bclr #CCLK,x:M_PDRD ; restart cycle 1420 P:0001A5 200033 lsl a ; shift control word to 1 bit 1421 ; to left 1422 end_send_codec 1423 P:0001A6 00000C rts 1424 1425 1426 1427 1428 ;**************************************************************************** 1429 ; SSI0_ISR.ASM Ver.2.0 1430 ; Example program to handle interrupts through 1431 ; the 56307 SSI0 to move audio through the CS4218 1432 ; 1433 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1434 ; Semiconductor Products Sector 1435 ; Digital Signal Processing Division 1436 ; 1437 ; 1438 ; History: 1439 ; 14 June 1996: RLR/LJD - ver 1.0 1440 ; 23 July 1997: BEA - ver 1.1 1441 ;****************************************************************************** 1442 1443 1444 ;----the actual interrupt service routines (ISRs) follow: 1445 1446 ;************************ SSI TRANSMIT ISR ********************************* 1447 ssi_txe_isr 1448 P:0001A7 013704 bclr #4,x:M_SSISR0 ; Read SSISR to clear exception flag 1449 ; explicitly clears underrun flag Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 ada_init.asm Page 9 1450 ssi_tx_isr 1451 P:0001A8 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1452 P:0001A9 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1453 P:0001AA 0501A0 move #1,m0 ; Modulus 2 buffer. 1454 P:0001AB 608900 move x:TX_PTR,r0 ; Load the pointer to the tx buffer. 1455 P:0001AC 000000 nop 1456 P:0001AD 000000 nop 1457 P:0001AE 000000 nop 1458 P:0001AF 07D83C movep x:(r0)+,x:M_TX00 ; SSI transfer data register. 1459 P:0001B0 600900 move r0,x:TX_PTR ; Update tx buffer pointer. 1460 P:0001B1 05FF20 move x:-(r7),m0 ; Restore m0. 1461 P:0001B2 60FF00 move x:-(r7),r0 ; Restore r0. 1462 P:0001B3 000004 rti 1463 1464 ;********************* SSI TRANSMIT LAST SLOT ISR ************************** 1465 ssi_txls_isr 1466 P:0001B4 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1467 P:0001B5 300400 move #TX_BUFF_BASE,r0 ; Reset pointer. 1468 P:0001B6 000000 nop 1469 P:0001B7 600900 move r0,x:TX_PTR ; Reset tx buffer pointer just in 1470 P:0001B8 000000 nop ; case it was corrupted. 1471 P:0001B9 60FF00 move x:-(r7),r0 ; Restore r0. 1472 P:0001BA 000004 rti 1473 1474 ;************************** SSI receive ISR ******************************** 1475 ssi_rxe_isr 1476 P:0001BB 013705 bclr #5,x:M_SSISR0 ; Read SSISR to clear exception flag 1477 ; explicitly clears overrun flag 1478 ssi_rx_isr 1479 P:0001BC 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1480 P:0001BD 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1481 P:0001BE 0501A0 move #1,m0 ; Modulus 2 buffer. 1482 P:0001BF 608800 move x:RX_PTR,r0 ; Load the pointer to the rx buffer. 1483 P:0001C0 000000 nop 1484 P:0001C1 000000 nop 1485 P:0001C2 000000 nop 1486 P:0001C3 075838 movep x:M_RX0,x:(r0)+ ; Read out received data to buffer. 1487 P:0001C4 600800 move r0,x:RX_PTR ; Update rx buffer pointer. 1488 P:0001C5 05FF20 move x:-(r7),m0 ; Restore m0. 1489 P:0001C6 60FF00 move x:-(r7),r0 ; Restore r0. 1490 P:0001C7 000004 rti 1491 1492 ;********************** SSI receive last slot ISR ************************** 1493 ssi_rxls_isr 1494 P:0001C8 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1495 P:0001C9 300000 move #RX_BUFF_BASE,r0 ; Reset rx buffer pointer just in 1496 ; case it was corrupted. 1497 P:0001CA 600800 move r0,x:RX_PTR ; Update rx buffer pointer. 1498 P:0001CB 60FF00 move x:-(r7),r0 ; Restore r0. 1499 P:0001CC 000004 rti 1500 1501 Y:000000 org y: 1502 Y:000000 mask dc $ffffff 1503 Y:000001 recv dc $000000 1504 Y:000002 dc $0 1505 Y:000003 text dc "Testing one two three" Motorola DSP56300 Assembler Version 6.2.0 99-12-02 18:32:12 pass_S~2.asm Page 10 1506 Y:00000A dc $0a0d00,$0 1507 Y:00000C text2 dc "123456789" 1508 Y:00000F dc $0a0d00,$0 1509 1510 ;echo 1511 end 0 Errors 0 Warnings