Motorola DSP56300 Assembler Version 6.2.0 99-03-20 15:37:04 u_memtst.asm Page 1 1 page 132,60,3,3, 2 ; 3 ; u_memtst.asm - unified memory test for 56303evm 4 ; 5 ; uses internal P:RAM to test Y: memory 6 ; 7 ; 12 June 90 - RLR: started... 8 ; 13 June 90 - RLR: added polish 9 ; 24 July 90 - RLR: more polish 10 ; 04 Sept 92 - RLR: changes for PC-Media Bd (Rev. 1) 11 ; 16 Apr 93 - RLR: changes for PC-Media Bd (Rev. 2.0) 12 ; 04 Oct 93 - RLR: added pattern update to host 13 ; 03 Apr 96 - JP: modified this for the 56303 14 ; 25 Apr 96 - LJD: modified start location and ouput location 15 ; 20 Jun 96 - PFS: modified for self loading and LED routines 16 17 ;*************************************************************************** 18 762 763 ;****************************************************************************** 764 765 if 1==1 766 X:000000 org X:0 767 000000 OUTPUT EQU * 768 MEM_FAIL_ADDR 769 X:000000 ds 1 ; OUTPUT+20 770 MEM_FAIL_EXPECT 771 X:000001 ds 1 ; OUTPUT+21 772 MEM_FAIL_RECEIVED_0 773 X:000002 ds 1 ; OUTPUT+22 774 MEM_FAIL_RECEIVED_1 775 X:000003 ds 1 ; OUTPUT+23 776 MEM_PASS_CNT 777 X:000004 ds 1 ; OUTPUT+24 778 000005 X_START EQU * 779 endif 780 781 782 783 001000 P_SIZE EQU $1000 ;4096 P: WORDS 784 000800 L_SIZE EQU $0800 ;2048 L: WORDS 785 008000 Y_SIZE EQU $8000 ;32K Y: WORDS 786 008000 Y_START EQU $8000 787 788 00000F MEM_LOOPS EQU $F ;repeat test 15 times 789 790 FFFFFF LINEAR EQU $FFFFFF ; linear addressing mode 791 008921 AAR0V EQU $008921 ; value programmed into AAR0 792 ; compare 9 most significant bits, look for a match w ith address 793 ; X:0000 0000 1xxx xxxx xxxx xxxx, no packing, no mux ing, Y enabled, 794 ; P and X disabled, AAR0 pin active low, asynchronous Motorola DSP56300 Assembler Version 6.2.0 99-03-20 15:37:04 u_memtst.asm Page 2 SRAM access 795 012421 BCRV EQU $012421 ; value programmed into BCR 796 ; (1 wait state for all AAR regions) 797 798 ;--------------------------------------------------------------------- 799 800 ;NOTE: This test will work only if the J9 jumper is set in 2<->3 position, 801 ; i.e. A14 is tied to the sram address bus, 32K available, AAR3 not connected 802 ; 803 ; note which locations are not tested, i.e. p:0..$18f, y:0..4 804 ; 805 ; n0 = starting address for internal P memory test 806 ; n1 = size of internal P memory (less used by this program) 807 ; n2 = starting address for internal L (X:Y) memory test 808 ; n3 = size of internal L memory (less used by the five MEM_* variables above) 809 ; n4 = starting address for external memory test (X:$8000 in this case) 810 ; n5 = size of external memory (32768 words, mapped from X:$8000 to X:$ffff) 811 812 P:000000 org P: 813 814 u_memtst 815 816 P:000000 08F4BD movep #$040004,x:M_PCTL ; set PLL for (5 x 16.9344) = 84.672 MHz 040004 817 P:000002 08F4B9 movep #AAR0V,x:M_AAR0 ; set up AAR0 as shown above 008921 818 P:000004 08F4BB movep #BCRV,x:M_BCR ; one ext. wait state for async srams 012421 819 P:000006 70F400 move #P_START,n0 ;starting int. P address, an approximate # for now 0000C4 820 P:000008 71F400 move #P_SIZE-P_START,n1 ;P memory size ($400 to $fff = ? or $?) 000F3C 821 P:00000A 3A0500 move #X_START,n2 ;starting int. L address **** 822 [u_memtst.asm 80]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 822 P:00000B 73F400 move #L_SIZE-X_START,n3 ;L memory size ($6 to $7ff = 2043 or $7fb) 0007FB **** 823 [u_memtst.asm 81]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 823 P:00000D 74F400 move #Y_START,n4 ;starting external address (x:$8000) 008000 **** 824 [u_memtst.asm 82]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 824 P:00000F 75F400 move #Y_SIZE,n5 ;ext. memory size ($8000 to $ffff = 32768 or $8000) 008000 825 **** 826 [u_memtst.asm 84]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 826 P:000011 07F43F movep #$0,x:M_PCRC ;disable both ESSIs and the SCI just to be safe 000000 **** 827 [u_memtst.asm 85]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 827 P:000013 07F42F movep #$0,x:M_PCRD 000000 **** 828 [u_memtst.asm 86]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 828 P:000015 07F41F movep #$0,x:M_PCRE 000000 829 830 P:000017 35001B clr b #0,r5 ;clear loop counter 831 P:000018 05F420 move #LINEAR,m0 ;again, we take no chances... FFFFFF Motorola DSP56300 Assembler Version 6.2.0 99-03-20 15:37:04 u_memtst.asm Page 3 832 833 P:00001A 570000 move b,X:MEM_FAIL_ADDR ; x:$0 834 P:00001B 570100 move b,X:MEM_FAIL_EXPECT ; x:$1 835 P:00001C 570200 move b,X:MEM_FAIL_RECEIVED_0 ; x:$2 836 P:00001D 570300 move b,X:MEM_FAIL_RECEIVED_1 ; x:$3 837 P:00001E 570400 move b,X:MEM_PASS_CNT ; x:$4 838 839 ; 840 mem_main 841 ;----------------------------------------------------------------------------- 842 ;--- fill all memory spaces with initial pattern --- 843 ;----------------------------------------------------------------------------- 844 **** 845 [u_memtst.asm 103]: WARNING --- Instruction cannot appear in interrupt vector locations (Opcode field) **** 845 [u_memtst.asm 103]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 845 P:00001F 060F90 dor #MEM_LOOPS,mem_loop 00002F **** 846 [u_memtst.asm 104]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 846 P:000021 63F400 move #YPATT,r3 ;point to the first test pattern 00008C 847 P:000023 650400 move r5,x:MEM_PASS_CNT 848 P:000024 231000 move n0,r0 ;load starting address of P into r0 849 P:000025 07DB84 move p:(r3)+,x0 ;load the pattern into x0 850 P:000026 208500 move x0,x1 ;and copy it to x1 as well 851 ;...(for writes to L:mem) **** 852 [u_memtst.asm 110]: WARNING --- Instruction cannot appear in interrupt vector locations (Opcode field) 852 P:000027 06D920 rep n1 ;fill P memory with initial pattern 853 P:000028 075884 move x0,p:(r0)+ 854 855 P:000029 235000 move n2,r0 ;load starting address of L into r0 **** 856 [u_memtst.asm 114]: WARNING --- Instruction cannot appear in interrupt vector locations (Opcode field) 856 P:00002A 06DB20 rep n3 ;fill L memory with initial pattern 857 P:00002B 425800 move x,L:(r0)+ 858 859 P:00002C 239000 move n4,r0 ;load starting address of external mem into r0 **** 860 [u_memtst.asm 118]: WARNING --- Instruction cannot appear in interrupt vector locations (Opcode field) 860 P:00002D 06DD20 rep n5 ;fill external memory with initial pattern 861 P:00002E 4C5800 move x0,y:(r0)+ 862 863 864 ;----------------------------------------------------------------------------- 865 ;--- check for expected data in each location and then replace with new --- 866 ;--- ...this also provides an address check since erroneous addressing will--- 867 ;--- ...cause the data to be written into incorrect locations and this will--- 868 ;--- ...be evident in the next pass reads. --- 869 ;----------------------------------------------------------------------------- **** 870 [u_memtst.asm 128]: WARNING --- Instruction cannot appear in interrupt vector locations (Opcode field) **** 870 [u_memtst.asm 128]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 870 P:00002F 063890 dor #PATTN,test_Ym ;test with all patterns 00001E 871 P:000031 231013 clr a n0,r0 ;r0 points to top of pram 872 P:000032 20AC1B clr b x1,a1 ;save the old value into a1 873 P:000033 20A800 move x1,a0 ;save the old value into a0 874 P:000034 20A900 move x1,b0 ;save the old value into b0 so that the cmp below 875 ;only takes into account b1 vs a1 876 P:000035 07DB84 move p:(r3)+,x0 ;get the next pattern into x0 Motorola DSP56300 Assembler Version 6.2.0 99-03-20 15:37:04 u_memtst.asm Page 4 877 P:000036 208500 move x0,x1 ;copy it to x1 as well 878 879 ; test P ram first **** 880 [u_memtst.asm 138]: WARNING --- Instruction cannot appear in interrupt vector locations (Opcode field) **** 880 [u_memtst.asm 138]: WARNING --- Two-word instruction assembled at odd address in interrupt vector locations (Opcode field) 880 P:000037 06D910 dor n1,int_p_loop ;test all P locations 000006 881 P:000039 07E08D move p:(r0),b1 ;read p:RAM -> b1 882 P:00003A 200005 cmp B,A ;was the data as expected??? 883 P:00003B 05208A bsne b1, Y:RAM -> b0 903 P:000049 200005 cmp B,A ;was the L: data as expected??? 904 P:00004A 05205B bsne