page 132,60,3,3, ; ; u_memtst.asm - unified memory test for 56303evm ; ; uses internal P:RAM to test Y: memory ; ; 12 June 90 - RLR: started... ; 13 June 90 - RLR: added polish ; 24 July 90 - RLR: more polish ; 04 Sept 92 - RLR: changes for PC-Media Bd (Rev. 1) ; 16 Apr 93 - RLR: changes for PC-Media Bd (Rev. 2.0) ; 04 Oct 93 - RLR: added pattern update to host ; 03 Apr 96 - JP: modified this for the 56303 ; 25 Apr 96 - LJD: modified start location and ouput location ; 20 Jun 96 - PFS: modified for self loading and LED routines ;*************************************************************************** nolist include 'ioequ.asm' include 'intequ.asm' include 'ada_equ.asm' ; include 'vectors.asm' list ;****************************************************************************** if STANDALONE==1 org X:0 OUTPUT EQU * MEM_FAIL_ADDR ds 1 ; OUTPUT+20 MEM_FAIL_EXPECT ds 1 ; OUTPUT+21 MEM_FAIL_RECEIVED_0 ds 1 ; OUTPUT+22 MEM_FAIL_RECEIVED_1 ds 1 ; OUTPUT+23 MEM_PASS_CNT ds 1 ; OUTPUT+24 X_START EQU * endif P_SIZE EQU $1000 ;4096 P: WORDS L_SIZE EQU $0800 ;2048 L: WORDS Y_SIZE EQU $8000 ;32K Y: WORDS Y_START EQU $8000 MEM_LOOPS EQU $F ;repeat test 15 times LINEAR EQU $FFFFFF ; linear addressing mode AAR0V EQU $008921 ; value programmed into AAR0 ; compare 9 most significant bits, look for a match with address ; X:0000 0000 1xxx xxxx xxxx xxxx, no packing, no muxing, Y enabled, ; P and X disabled, AAR0 pin active low, asynchronous SRAM access BCRV EQU $012421 ; value programmed into BCR ; (1 wait state for all AAR regions) ;--------------------------------------------------------------------- ;NOTE: This test will work only if the J9 jumper is set in 2<->3 position, ; i.e. A14 is tied to the sram address bus, 32K available, AAR3 not connected ; ; note which locations are not tested, i.e. p:0..$18f, y:0..4 ; ; n0 = starting address for internal P memory test ; n1 = size of internal P memory (less used by this program) ; n2 = starting address for internal L (X:Y) memory test ; n3 = size of internal L memory (less used by the five MEM_* variables above) ; n4 = starting address for external memory test (X:$8000 in this case) ; n5 = size of external memory (32768 words, mapped from X:$8000 to X:$ffff) org P: u_memtst movep #$040004,x:M_PCTL ; set PLL for (5 x 16.9344) = 84.672 MHz movep #AAR0V,x:M_AAR0 ; set up AAR0 as shown above movep #BCRV,x:M_BCR ; one ext. wait state for async srams move #P_START,n0 ;starting int. P address, an approximate # for now move #P_SIZE-P_START,n1 ;P memory size ($400 to $fff = ? or $?) move #X_START,n2 ;starting int. L address move #L_SIZE-X_START,n3 ;L memory size ($6 to $7ff = 2043 or $7fb) move #Y_START,n4 ;starting external address (x:$8000) move #Y_SIZE,n5 ;ext. memory size ($8000 to $ffff = 32768 or $8000) movep #$0,x:M_PCRC ;disable both ESSIs and the SCI just to be safe movep #$0,x:M_PCRD movep #$0,x:M_PCRE clr b #0,r5 ;clear loop counter move #LINEAR,m0 ;again, we take no chances... move b,X:MEM_FAIL_ADDR ; x:$0 move b,X:MEM_FAIL_EXPECT ; x:$1 move b,X:MEM_FAIL_RECEIVED_0 ; x:$2 move b,X:MEM_FAIL_RECEIVED_1 ; x:$3 move b,X:MEM_PASS_CNT ; x:$4 ; mem_main ;----------------------------------------------------------------------------- ;--- fill all memory spaces with initial pattern --- ;----------------------------------------------------------------------------- dor #MEM_LOOPS,mem_loop move #YPATT,r3 ;point to the first test pattern move r5,x:MEM_PASS_CNT move n0,r0 ;load starting address of P into r0 move p:(r3)+,x0 ;load the pattern into x0 move x0,x1 ;and copy it to x1 as well ;...(for writes to L:mem) rep n1 ;fill P memory with initial pattern move x0,p:(r0)+ move n2,r0 ;load starting address of L into r0 rep n3 ;fill L memory with initial pattern move x,L:(r0)+ move n4,r0 ;load starting address of external mem into r0 rep n5 ;fill external memory with initial pattern move x0,y:(r0)+ ;----------------------------------------------------------------------------- ;--- check for expected data in each location and then replace with new --- ;--- ...this also provides an address check since erroneous addressing will--- ;--- ...cause the data to be written into incorrect locations and this will--- ;--- ...be evident in the next pass reads. --- ;----------------------------------------------------------------------------- dor #PATTN,test_Ym ;test with all patterns clr a n0,r0 ;r0 points to top of pram clr b x1,a1 ;save the old value into a1 move x1,a0 ;save the old value into a0 move x1,b0 ;save the old value into b0 so that the cmp below ;only takes into account b1 vs a1 move p:(r3)+,x0 ;get the next pattern into x0 move x0,x1 ;copy it to x1 as well ; test P ram first dor n1,int_p_loop ;test all P locations move p:(r0),b1 ;read p:RAM -> b1 cmp B,A ;was the data as expected??? bsne b1, Y:RAM -> b0 cmp B,A ;was the L: data as expected??? bsne