;***************************************************************************
;QS_ST.ASM : WILL PASS AUDIO STRAIGHT THROUGH        
;***************************************************************************
      nolist
      include 'ioequ.asm'
      include 'intequ.asm'
      include 'ada_equ.asm'
      include 'vectors.asm'  
      list
  
;******************************************************************************

;---Buffer for talking to the CS4215

       org    x:0
RX_BUFF_BASE	equ     *
RX_data_1_2	ds	1	;data time slot 1/2 for RX ISR
RX_data_3_4	ds	1	;data time slot 3/4 for RX ISR
RX_data_5_6	ds	1	;data time slot 5/6 for RX ISR
RX_data_7_8	ds	1	;data time slot 7/8 for RX ISR

TX_BUFF_BASE	equ	*
TX_data_1_2	ds	1	;data time slot 1/2 for TX ISR
TX_data_3_4	ds	1	;data time slot 3/4 for TX ISR
TX_data_5_6	ds	1	;data time slot 5/6 for TX ISR
TX_data_7_8	ds	1	;data time slot 7/8 for TX ISR

RX_PTR          ds      1	; Pointer for rx buffer
TX_PTR          ds      1	; Pointer for tx buffer

;TONE_OUTPUT     EQU     HEADPHONE_EN+LINEOUT_EN+(4*LEFT_ATTN)+(4*RIGHT_ATTN)   
;TONE_INPUT      EQU     MIC_IN_SELECT+(15*MONITOR_ATTN)
;CTRL_WD_12	equ	NO_PREAMP+HI_PASS_FILT+SAMP_RATE_48+STEREO+DATA_16   ;CLB=0
;CTRL_WD_34	equ	IMMED_3STATE+XTAL1_SELECT+BITS_64+CODEC_MASTER
;CTRL_WD_56	equ	$000000
;CTRL_WD_78	equ	$000000

CTRL_WD_12      equ     MIN_LEFT_ATTN+MIN_RIGHT_ATTN+LIN2+RIN2
CTRL_WD_34      equ     MIN_LEFT_GAIN+MIN_RIGHT_GAIN


        org     p:$100
START
main
        movep   #$040003,x:M_PCTL    ; set PLL for MPY of 4X
        movep   #$012421,x:M_BCR   ; set up one ext. wait state for all AAR areas
        ori     #3,mr           ;mask interrupts
        movec   #0,sp           ;clear hardware stack pointer
        move    #0,omr          ;operating mode 0
        move    #$40,r6         ; initialise stack pointer
        move    #-1,m6          ; linear addressing
        jsr     ada_init        ; initialize codec


; initialize SCI

; 10-bit asynchronous mode
; enable reciever and transmitter
	movep	#$000302,x:M_SCR	; SCI control register

; enable tx and rx pins
	movep	#$000003,x:M_PCRE	; Port E Control Register

; Reciever/Transmitter clocks use external clock from SCLK
	movep	#$00C000,x:M_SCCR	; SCI Clock Control Register

	move	#text,r5
	jsr print



loop_1
        
        jset    #2,x:M_SSISR0,*    ;wait for frame sync to pass
        jclr    #2,x:M_SSISR0,*    ;wait for frame sync

        move    x:RX_BUFF_BASE,a        ;receive left
        move    x:RX_BUFF_BASE+1,b      ;receive right
        jsr     process_stereo
        move    a,x:TX_BUFF_BASE        ;transmit left
        move    b,x:TX_BUFF_BASE+1      ;transmit right
        
        move    #CTRL_WD_12,y0 ;set up control words
        move    y0,x:TX_BUFF_BASE+2
        move    #CTRL_WD_12,y0
        move    y0,x:TX_BUFF_BASE+3

        jmp     loop_1

process_stereo
        nop
        nop
        nop
        rts


;print subroutine takes address in register r5
print
	move a,x0
prbegin	move y:(r5)+,y0

	move	#$00ffff,a
	cmp	y0,a
;	cmp	#$00ffff,y0	;check to see if done (char=$00)
	bgt	prend
	jclr 	#1,x:M_SSR,*		;wait for tx to finish
	jclr 	#0,x:M_SSR,*		;wait for tx to finish
	move y0,x:M_STXH		; send high byte

	move	#$001111,a
	and	y0,a
	move	a,y0
;	cmp	#$0000ff,y0	;check to see if done ($00)
	bgt	prend
	jclr 	#1,x:M_SSR,*		;wait for tx to finish
	jclr 	#0,x:M_SSR,*		;wait for tx to finish
	move y0,x:M_STXM		; send mid byte

	jclr 	#1,x:M_SSR,*		;wait for tx to finish
	jclr 	#0,x:M_SSR,*		;wait for tx to finish
	move y0,x:M_STXL		; send low byte

	bra	prbegin
prend	move x0,a
	rts


        include 'ada_init.asm'

      org     y:
text
	dc	"Testing one two three"
	dc	$0
	dc	"12345"
echo
        end