Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 pass_s~6.asm Page 1 1 ;*************************************************************************** 2 ;QS_ST.ASM : WILL PASS AUDIO STRAIGHT THROUGH 3 ;*************************************************************************** 1067 1068 ;****************************************************************************** 1069 1070 ;---Buffer for talking to the CS4215 1071 1072 X:000000 org x:0 1073 RX_BUFF_BASE 1074 000000 equ * 1075 RX_data_1_2 1076 X:000000 ds 1 ;data time slot 1/2 for RX ISR 1077 RX_data_3_4 1078 X:000001 ds 1 ;data time slot 3/4 for RX ISR 1079 RX_data_5_6 1080 X:000002 ds 1 ;data time slot 5/6 for RX ISR 1081 RX_data_7_8 1082 X:000003 ds 1 ;data time slot 7/8 for RX ISR 1083 1084 TX_BUFF_BASE 1085 000004 equ * 1086 TX_data_1_2 1087 X:000004 ds 1 ;data time slot 1/2 for TX ISR 1088 TX_data_3_4 1089 X:000005 ds 1 ;data time slot 3/4 for TX ISR 1090 TX_data_5_6 1091 X:000006 ds 1 ;data time slot 5/6 for TX ISR 1092 TX_data_7_8 1093 X:000007 ds 1 ;data time slot 7/8 for TX ISR 1094 1095 X:000008 RX_PTR ds 1 ; Pointer for rx buffer 1096 X:000009 TX_PTR ds 1 ; Pointer for tx buffer 1097 1098 ;TONE_OUTPUT EQU HEADPHONE_EN+LINEOUT_EN+(4*LEFT_ATTN)+(4*RIGHT_ATTN) 1099 ;TONE_INPUT EQU MIC_IN_SELECT+(15*MONITOR_ATTN) 1100 ;CTRL_WD_12 equ NO_PREAMP+HI_PASS_FILT+SAMP_RATE_48+STEREO+DATA_16 ;CLB=0 1101 ;CTRL_WD_34 equ IMMED_3STATE+XTAL1_SELECT+BITS_64+CODEC_MASTER 1102 ;CTRL_WD_56 equ $000000 1103 ;CTRL_WD_78 equ $000000 1104 1105 000300 CTRL_WD_12 equ MIN_LEFT_ATTN+MIN_RIGHT_ATTN+LIN2+RIN2 1106 000000 CTRL_WD_34 equ MIN_LEFT_GAIN+MIN_RIGHT_GAIN 1107 1108 1109 P:000050 org p:$50 ;SCI Recieve Data Interrupt 1110 P:000050 0BF080 jsr ISCIRD 000154 1111 1112 P:000100 org p:$100 1113 START 1114 main 1115 P:000100 08F4BD movep #$040003,x:M_PCTL ; set PLL for MPY of 4X 040003 1116 P:000102 08F4BB movep #$012421,x:M_BCR ; set up one ext. wait state for all AAR areas 012421 Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 pass_s~6.asm Page 2 1117 P:000104 0003F8 ori #3,mr ;mask interrupts 1118 P:000105 0500BB movec #0,sp ;clear hardware stack pointer 1119 P:000106 0500BA move #0,omr ;operating mode 0 1120 P:000107 364000 move #$40,r6 ; initialise stack pointer 1121 P:000108 05F426 move #-1,m6 ; linear addressing FFFFFF 1122 P:00010A 0BF080 jsr ada_init ; initialize codec 00019C 1123 1124 1125 ; initialize SCI 1126 ; 10-bit asynchronous mode 1127 ; enable reciever and transmitter 1128 P:00010C 07F41C movep #$000B02,x:M_SCR ; SCI control register 000B02 1129 ; set interrupt priority for SCI RECV to 1 1130 P:00010E 56F000 move x:M_IPRP,a FFFFFE 1131 ; enable tx and rx pins 1132 P:000110 07F41F movep #$000003,x:M_PCRE ; Port E Control Register 000003 1133 P:000112 0140C2 or #000080,a ; interrupt priority 2 000050 1134 ; Reciever/Transmitter clocks use external clock from SCLK 1135 P:000114 07F41B movep #$00C000,x:M_SCCR ; SCI Clock Control Register 00C000 1136 P:000116 567000 move a,x:M_IPRP ; interrupt priority peripheral FFFFFE 1137 1138 ;print a greeting and instructions 1139 P:000118 65F400 move #greet,r5 000001 1140 P:00011A 0BF080 jsr print 000133 1141 1142 ; move #$123456,a1 1143 ; move #$789abc,a0 1144 ; move a,y0 1145 ; debug 1146 1147 1148 loop_1 1149 1150 P:00011C 01B7A2 jset #2,x:M_SSISR0,* ;wait for frame sync to pass 00011C 1151 P:00011E 01B782 jclr #2,x:M_SSISR0,* ;wait for frame sync 00011E 1152 1153 P:000120 568000 move x:RX_BUFF_BASE,a ;receive left 1154 P:000121 578100 move x:RX_BUFF_BASE+1,b ;receive right 1155 P:000122 0BF080 jsr process_stereo 00012D 1156 P:000124 560400 move a,x:TX_BUFF_BASE ;transmit left 1157 P:000125 570500 move b,x:TX_BUFF_BASE+1 ;transmit right 1158 1159 P:000126 46F400 move #CTRL_WD_12,y0 ;set up control words Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 pass_s~6.asm Page 3 000300 1160 P:000128 460600 move y0,x:TX_BUFF_BASE+2 1161 P:000129 46F400 move #CTRL_WD_12,y0 000300 1162 P:00012B 460700 move y0,x:TX_BUFF_BASE+3 1163 1164 P:00012C 0C011C jmp loop_1 1165 1166 process_stereo 1167 P:00012D 4EF000 move y:mask,y0 000000 1168 P:00012F 200056 and y0,a 1169 P:000130 20005E and y0,b 1170 P:000131 000000 nop 1171 P:000132 00000C rts 1172 1173 1174 ;print subroutine takes address in register r5 1175 ;exits when most significant byte is zero 1176 ;ignores zeros in lower bytes 1177 ; clobbers accumulator A and B and register r5 1178 print 1179 P:000133 5EDD00 prbegin move y:(r5)+,a 1180 ; cmp #$00ffff,a ;check to see if done (char=$00) 1181 ; blt prend 1182 P:000134 014085 cmp #$000000,a ;check to see if done (char=$00) 1183 P:000135 0D104A beq prend 00001E 1184 P:000137 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 000137 1185 P:000139 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 000139 1186 P:00013B 567000 move a,x:M_STXH ; send high byte FFFF97 1187 P:00013D 0140C6 and #$00ffff,a 00FFFF 1188 P:00013F 0140C5 cmp #$0000ff,a 0000FF 1189 P:000141 0597D2 blt prbegin 1190 P:000142 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 000142 1191 P:000144 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 000144 1192 P:000146 567000 move a,x:M_STXM ; send mid byte FFFF96 1193 P:000148 0140C6 and #$0000ff,a 0000FF 1194 P:00014A 014085 cmp #$000000,a 1195 P:00014B 0597C8 blt prbegin 1196 P:00014C 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 00014C 1197 P:00014E 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 00014E 1198 P:000150 567000 move a,x:M_STXL ; send low byte FFFF95 1199 P:000152 050FC1 bra prbegin Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 pass_s~6.asm Page 4 1200 P:000153 00000C prend rts 1201 1202 1203 ; the SCI interrupt is triggered when a character is received 1204 ; this function takes the character, checks to make sure it is 1205 ; in the correct range (1-9, A-G, a-g) prints a message and 1206 ; modifies the output mask for that number of bits 1207 P:000154 21C600 ISCIRD move a,y0 ;back up A 1208 P:000155 56F000 move x:M_SRXL,a FFFF98 1209 P:000157 017185 cmp #$31,a ; >='1' 1210 P:000158 0D1049 blt iscend 000042 1211 P:00015A 017A85 cmp #$3A,a ; <='9' 1212 P:00015B 0D1049 blt iscnum 000015 1213 1214 P:00015D 0140C5 cmp #$40,a ; >='A' 000040 1215 P:00015F 0D1049 blt iscend 00003B 1216 P:000161 0140C5 cmp #$48,a ; <='G' 000048 1217 P:000163 0D1049 blt isclet 00000E 1218 P:000165 0140C5 cmp #$60,a ; >='a' 000060 1219 P:000167 0D1049 blt iscend 000033 1220 P:000169 0140C5 cmp #$67,a ; <='g' 000067 1221 P:00016B 0D1047 bgt iscend 00002F 1222 P:00016D 016084 sub #$20,a 1223 P:00016E 0D10C0 bra isclet 000003 1224 1225 P:000170 014780 iscnum add #$07,a 1226 P:000171 014980 isclet add #$09,a 1227 1228 P:000172 019381 isciup jclr #1,x:M_SSR,* ;wait for tx to finish 000172 1229 P:000174 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 000174 1230 P:000176 07F415 movep #$0d,x:M_STXL ;print LF 00000D 1231 P:000178 2F8000 move #$800000,b ;initial mask 1232 P:000179 5E7000 move a,y:mask ;hold onto value temporarially 000000 1233 P:00017B 0140C4 sub #$41,a ; ammount to shift mask 000041 1234 P:00017D 21C400 move a,x0 1235 P:00017E 0C1E79 asr x0,b,b ; shift the mask 1236 P:00017F 5EF000 move y:mask,a 000000 1237 P:000181 5F7000 move b,y:mask Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 pass_s~6.asm Page 5 000000 1238 1239 P:000183 015084 sub #$10,a 1240 P:000184 017A85 cmp #$3A,a ; is a 10 digit? 1241 P:000185 0D1049 blt isci0 000009 1242 1243 P:000187 019381 isci1 jclr #1,x:M_SSR,* ;wait for tx to finish 000187 1244 P:000189 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 000189 1245 P:00018B 07F415 movep #$31,x:M_STXL 000031 1246 P:00018D 014A84 sub #$0a,a 1247 1248 P:00018E 019381 isci0 jclr #1,x:M_SSR,* ;wait for tx to finish 00018E 1249 P:000190 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 000190 1250 P:000192 567000 move a,x:M_STXL FFFF95 1251 P:000194 019381 jclr #1,x:M_SSR,* ;wait for tx to finish 000194 1252 P:000196 019380 jclr #0,x:M_SSR,* ;wait for tx to finish 000196 1253 P:000198 07F415 movep #$20,x:M_STXL 000020 1254 1255 P:00019A 20CE00 iscend move y0,a ;restore A 1256 P:00019B 000004 rti 1257 1258 1259 1260 1261 include 'ada_init.asm' 1262 page 132,60 1263 ;************************************************************************** 1264 ; ADA_INIT.ASM Ver 1.2 1265 ; Example program to initialize the CS4218 1266 ; 1267 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1268 ; Semiconductor Products Sector 1269 ; Wireless Signal Processing Division 1270 ; 1271 ; History: 1272 ; 14 June 1996: RLR/LJD - ver 1.0 1273 ; 21 July 1997: BEA - ver 1.1 1274 ; 23 Sept 1998: TTL - ver 1.2 1275 ;************************************************************************** 1276 X:00000A org x: 1277 1278 ; Codec control constants 1279 X:00000A CTRL_WD_HI ds 1 1280 X:00000B CTRL_WD_LO ds 1 1281 1282 Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 ada_init.asm Page 6 1283 ; GPIO pin constants 1284 1285 ; ESSI0 - audio data GPIO mode 1286 ; DSP CODEC 1287 ; --------------------------- 1288 CODEC_RESET 1289 000000 equ 0 ; bit0 SC00 ---> CODEC_RESET~ 1290 1291 ; ESSI1 - control data GPIO Mode 1292 ; DSP CODEC 1293 ;---------------------------- 1294 000000 CCS equ 0 ; bit0 SC10 ---> CCS~ 1295 000001 CCLK equ 1 ; bit1 SC11 ---> CCLK 1296 000002 CDIN equ 2 ; bit2 SC12 ---> CDIN 1297 1298 ;************************************************************************** 1299 ; Initialize the CS4218 codec 1300 ; --------------------------- 1301 ; Serial Mode 4 (SM4), DSP Slave/Codec Master, 32-bits per frame 1302 ; 1303 ; After a reset, the control port must be written once to initialize it 1304 ; if the port will be accessed to read or write control bits. The initial 1305 ; write is a "dummy" write since the data is ignored by the codec. A second 1306 ; write is needed to configure the codec as desired. Then, the control port 1307 ; only needs to be written to when a change is desired, or to obtain status 1308 ; information. 1309 ; 1310 ; Although only 23 bits contain useful data in CDIN, a minimum of 31 bits 1311 ; must be written. 1312 ; 1313 ; CDIN 1314 ;------------------------------------------------ 1315 ; bit 31 0 1316 ;------------------------------------------------ 1317 ; bit 30 mask interrupt 1318 ; 0=no mask on MF5:\INT pin 1319 ; 1=mask on MF5:\INT pin 1320 ;------------------------------------------------ 1321 ; bit 29 DO1 1322 ;------------------------------------------------ 1323 ; bits 28-24 left output D/A sttenuation (1.5dB steps) 1324 ; 00000=No attenuation 0dB 1325 ; 11111=Max attenuation -46.5dB 1326 ;------------------------------------------------ 1327 ; bits 23-19 right output D/A attenuation (1.5dB steps) 1328 ; 00000=No attenuation 0dB 1329 ; 11111=Max attenuation -46.5dB 1330 ;------------------------------------------------ 1331 ; bit 18 mute D/A outputs 1332 ; 0=outputs ON 1333 ; 1=outputs MUTED 1334 ;------------------------------------------------ 1335 ; bit 17 input mux, left select 1336 ; 0=RIN1 1337 ; 1=RIN2 (used on EVM) 1338 ;------------------------------------------------ Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 ada_init.asm Page 7 1339 ; bit 16 input mux, right select 1340 ; 0=LIN1 1341 ; 1=LIN2 (used on EVM) 1342 ;------------------------------------------------ 1343 ; bits 15-12 left input A/D gain (1.5dB steps) 1344 ; 0000=No gain 0dB 1345 ; 1111=Max gain +22.5dB 1346 ;------------------------------------------------ 1347 ; bits 11-8 right input A/D gain (1.5dB steps) 1348 ; 0000=No gain 0dB 1349 ; 1111=Max gain +22.5dB 1350 ;------------------------------------------------ 1351 ; bits 7-0 00000000 1352 ;------------------------------------------------ 1353 ;************************************************************************** 1354 1355 1356 P:00019C org p: 1357 ada_init 1358 1359 ; reset ESSI ports 1360 P:00019C 07F43F movep #$0000,x:M_PCRC ; reset ESSI0 port 000000 1361 P:00019E 07F42F movep #$0000,x:M_PCRD ; reset ESSI1 port 000000 1362 1363 ; Set Control Register A and B 1364 P:0001A0 07F435 movep #$101807,x:M_CRA0 ; 12.288MHz/16 = 768KHz SCLK 101807 1365 ; prescale modulus = 8 1366 ; frame rate divider = 2 1367 ; 16-bits per word 1368 ; 32-bits per frame 1369 ; 16-bit data aligned to bit 23 1370 1371 P:0001A2 07F436 movep #$ff330c,x:M_CRB0 ; Enable REIE,TEIE,RLIE,TLIE, FF330C 1372 ; RIE,TIE,RE,TE0 1373 ; network mode, synchronous, 1374 ; out on rising/in on falling 1375 ; shift MSB first 1376 ; external clock source drives SCK 1377 ; (codec is master) 1378 ; RX frame sync pulses active for 1379 ; 1 bit clock immediately before 1380 ; transfer period 1381 ; positive frame sync polarity 1382 ; frame sync length is 1-bit 1383 1384 ; Configure GPIO pins -- (functionality and direction ) 1385 P:0001A4 07F43F movep #$0000,x:M_PCRC ; Enable GPIO pin 0 SC00=CODEC_RESET 000000 1386 P:0001A6 07F42F movep #$0000,x:M_PCRD ; Enable GPIO CSS (pin 0),CCLK (pin 1), CDIN (pin 2) 000000 1387 Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 ada_init.asm Page 8 1388 P:0001A8 07F43E movep #$0001,x:M_PRRC ; set PC0=CODEC_RESET~ as output 000001 1389 P:0001AA 07F42E movep #$0007,x:M_PRRD ; set PD0=CCS~ as output 000007 1390 ; set PD1=CCLK as output 1391 ; set PD2=CDIN as output 1392 1393 ; Codec Reset 1394 P:0001AC 013D00 bclr #CODEC_RESET,x:M_PDRC ; assert CODEC_RESET~ 1395 P:0001AD 012D00 bclr #CCS,x:M_PDRD ; assert CCS~ -- allows control register to be writte n to 1396 1397 ; Delay to allow Codec to reset 1398 P:0001AE 06E883 do #1000,_delay_loop 0001B1 1399 P:0001B0 06E8A3 rep #1000 ; minimum 50 ms delay 1400 P:0001B1 000000 nop 1401 _delay_loop 1402 1403 1404 ; Setting up to send Codec control information 1405 P:0001B2 013D20 bset #CODEC_RESET,x:M_PDRC ; deassert CODEC_RESET~ 1406 1407 1408 ; Sending control words 1409 set_control 1410 P:0001B3 44F400 move #CTRL_WD_12,x0 ; transfer control value to control variable 000300 1411 P:0001B5 440A00 move x0,x:CTRL_WD_HI 1412 P:0001B6 240000 move #CTRL_WD_34,x0 1413 P:0001B7 440B00 move x0,x:CTRL_WD_LO 1414 P:0001B8 0BF080 jsr codec_control ; send in dummy control information 0001C2 1415 P:0001BA 0BF080 jsr codec_control ; send in correct control information 0001C2 1416 1417 1418 ; Set and enable interrupts 1419 P:0001BC 08F4BE movep #$000c,x:M_IPRP ; set interrupt priority level for ESSI0 to 3 00000C 1420 P:0001BE 00FCB8 andi #$fc,mr ; enable interrupts 1421 1422 ; Set ESSI functionality 1423 P:0001BF 07F43F movep #$003e,x:M_PCRC ; enable ESSI0 except SC00=CODEC_RESET 00003E 1424 1425 P:0001C1 00000C rts 1426 1427 1428 ;------------------------------------------------------------- 1429 ; codec_control routine 1430 ; Input: CTRL_WD_LO and CTRL_WD_HI 1431 ; Output: CDIN 1432 ; Description: Used to send control information to CODEC 1433 ; NOTE: does not preserve the 'a' register. 1434 ;------------------------------------------------------------- Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 ada_init.asm Page 9 1435 codec_control 1436 P:0001C2 200013 clr a 1437 P:0001C3 012D00 bclr #CCS,x:M_PDRD ; assert CCS 1438 P:0001C4 548A00 move x:CTRL_WD_HI,a1 ; upper 16 bits of control data 1439 P:0001C5 0BF080 jsr send_codec ; shift out upper control word 0001CC 1440 P:0001C7 548B00 move x:CTRL_WD_LO,a1 ; lower 16 bits of control data 1441 P:0001C8 0BF080 jsr send_codec ; shift out lower control word 0001CC 1442 P:0001CA 012D20 bset #CCS,x:M_PDRD ; deassert CCS 1443 P:0001CB 00000C rts 1444 1445 1446 ;--------------------------------------------------------------- 1447 ; send_codec routine 1448 ; Input: a1 containing control information 1449 ; Output: sends bits to CDIN 1450 ; Description: Determines bits to send to CDIN 1451 ;--------------------------------------------------------------- 1452 1453 send_codec 1454 P:0001CC 061080 do #16,end_send_codec ; 16 bits per word 0001D8 1455 P:0001CE 012D21 bset #CCLK,x:M_PDRD ; toggle CCLK clock high 1456 P:0001CF 0ACC17 jclr #23,a1,bit_low ; test msb 0001D4 1457 P:0001D1 012D22 bset #CDIN,x:M_PDRD ; send high into CDIN 1458 P:0001D2 0AF080 jmp continue 0001D5 1459 bit_low 1460 P:0001D4 012D02 bclr #CDIN,x:M_PDRD ; send low into CDIN 1461 continue 1462 P:0001D5 0602A0 rep #2 ; delay 1463 P:0001D6 000000 nop 1464 P:0001D7 012D01 bclr #CCLK,x:M_PDRD ; restart cycle 1465 P:0001D8 200033 lsl a ; shift control word to 1 bit 1466 ; to left 1467 end_send_codec 1468 P:0001D9 00000C rts 1469 1470 1471 1472 1473 ;**************************************************************************** 1474 ; SSI0_ISR.ASM Ver.2.0 1475 ; Example program to handle interrupts through 1476 ; the 56307 SSI0 to move audio through the CS4218 1477 ; 1478 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1479 ; Semiconductor Products Sector 1480 ; Digital Signal Processing Division 1481 ; 1482 ; 1483 ; History: 1484 ; 14 June 1996: RLR/LJD - ver 1.0 1485 ; 23 July 1997: BEA - ver 1.1 Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 ada_init.asm Page 10 1486 ;****************************************************************************** 1487 1488 1489 ;----the actual interrupt service routines (ISRs) follow: 1490 1491 ;************************ SSI TRANSMIT ISR ********************************* 1492 ssi_txe_isr 1493 P:0001DA 013704 bclr #4,x:M_SSISR0 ; Read SSISR to clear exception flag 1494 ; explicitly clears underrun flag 1495 ssi_tx_isr 1496 P:0001DB 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1497 P:0001DC 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1498 P:0001DD 0501A0 move #1,m0 ; Modulus 2 buffer. 1499 P:0001DE 608900 move x:TX_PTR,r0 ; Load the pointer to the tx buffer. 1500 P:0001DF 000000 nop 1501 P:0001E0 000000 nop 1502 P:0001E1 000000 nop 1503 P:0001E2 07D83C movep x:(r0)+,x:M_TX00 ; SSI transfer data register. 1504 P:0001E3 600900 move r0,x:TX_PTR ; Update tx buffer pointer. 1505 P:0001E4 05FF20 move x:-(r7),m0 ; Restore m0. 1506 P:0001E5 60FF00 move x:-(r7),r0 ; Restore r0. 1507 P:0001E6 000004 rti 1508 1509 ;********************* SSI TRANSMIT LAST SLOT ISR ************************** 1510 ssi_txls_isr 1511 P:0001E7 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1512 P:0001E8 300400 move #TX_BUFF_BASE,r0 ; Reset pointer. 1513 P:0001E9 000000 nop 1514 P:0001EA 600900 move r0,x:TX_PTR ; Reset tx buffer pointer just in 1515 P:0001EB 000000 nop ; case it was corrupted. 1516 P:0001EC 60FF00 move x:-(r7),r0 ; Restore r0. 1517 P:0001ED 000004 rti 1518 1519 ;************************** SSI receive ISR ******************************** 1520 ssi_rxe_isr 1521 P:0001EE 013705 bclr #5,x:M_SSISR0 ; Read SSISR to clear exception flag 1522 ; explicitly clears overrun flag 1523 ssi_rx_isr 1524 P:0001EF 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1525 P:0001F0 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1526 P:0001F1 0501A0 move #1,m0 ; Modulus 2 buffer. 1527 P:0001F2 608800 move x:RX_PTR,r0 ; Load the pointer to the rx buffer. 1528 P:0001F3 000000 nop 1529 P:0001F4 000000 nop 1530 P:0001F5 000000 nop 1531 P:0001F6 075838 movep x:M_RX0,x:(r0)+ ; Read out received data to buffer. 1532 P:0001F7 600800 move r0,x:RX_PTR ; Update rx buffer pointer. 1533 P:0001F8 05FF20 move x:-(r7),m0 ; Restore m0. 1534 P:0001F9 60FF00 move x:-(r7),r0 ; Restore r0. 1535 P:0001FA 000004 rti 1536 1537 ;********************** SSI receive last slot ISR ************************** 1538 ssi_rxls_isr 1539 P:0001FB 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1540 P:0001FC 300000 move #RX_BUFF_BASE,r0 ; Reset rx buffer pointer just in 1541 ; case it was corrupted. Motorola DSP56300 Assembler Version 6.2.0 99-12-03 12:21:52 ada_init.asm Page 11 1542 P:0001FD 600800 move r0,x:RX_PTR ; Update rx buffer pointer. 1543 P:0001FE 60FF00 move x:-(r7),r0 ; Restore r0. 1544 P:0001FF 000004 rti 1545 1546 Y:000000 org y: 1547 Y:000000 mask dc $ffffff 1548 Y:000001 greet dc $0a0d00 1549 Y:000002 dc "This program demonstrates audio sampling on the " 1550 Y:000012 dc $0a0d00 1551 Y:000013 dc "Motorola DSP56303 at 1 to 16 bits." 1552 Y:00001F dc $0a0d00 1553 Y:000020 dc "Attach the audio input to the Line-In jack and speakers/headphones" 1554 Y:000036 dc $0a0d00 1555 Y:000037 dc "to the Headphone-Out jack. " 1556 Y:000041 dc $0a0d00 1557 Y:000042 dc $0a0d00 1558 Y:000043 dc "Type 1-9 or A-G to get the different sampling characteristics" 1559 Y:000058 dc $0a0d00 1560 Y:000059 dc "1=1 bit, G=16 bit" 1561 Y:00005F dc $0a0d00,$0a0d00 1562 Y:000061 dc "Sampling resolution (bits) :" 1563 Y:00006B dc $0a0d00 1564 Y:00006C dc "16 " 1565 Y:00006D dc $0 1566 Y:00006E crlf dc $0a0d00,$0 1567 1568 ;echo 1569 end 0 Errors 0 Warnings