Motorola DSP56300 Assembler Version 6.2.0 99-09-08 10:58:29 echo2.asm Page 1 1 ;*************************************************************************** 2 1067 1068 ;****************************************************************************** 1069 1070 ;---Buffer for talking to the CS4218 1071 1072 X:000000 org x:$0 1073 RX_BUFF_BASE 1074 000000 equ * 1075 RX_data_1_2 1076 X:000000 ds 1 ; data time slot 1/2 for RX ISR (left audio) 1077 RX_data_3_4 1078 X:000001 ds 1 ; data time slot 3/4 for RX ISR (right audio) 1079 1080 TX_BUFF_BASE 1081 000002 equ * 1082 TX_data_1_2 1083 X:000002 ds 1 ; data time slot 1/2 for TX ISR (left audio) 1084 TX_data_3_4 1085 X:000003 ds 1 ; data time slot 3/4 for TX ISR (right audio) 1086 1087 X:000004 RX_PTR ds 1 ; Pointer for rx buffer 1088 X:000005 TX_PTR ds 1 ; Pointer for tx buffer 1089 1090 000300 CTRL_WD_12 equ MIN_LEFT_ATTN+MIN_RIGHT_ATTN+LIN2+RIN2 1091 000000 CTRL_WD_34 equ MIN_LEFT_GAIN+MIN_RIGHT_GAIN 1092 1093 1094 1095 1096 P:000100 org p:$100 1097 START 1098 main 1099 P:000100 08F4BD movep #$040006,x:M_PCTL ; PLL 7 X 12.288 = 86.016MHz 040006 1100 P:000102 0003F8 ori #3,mr ; mask interrupts 1101 P:000103 0500BB movec #0,sp ; clear hardware stack pointer 1102 P:000104 0500BA move #0,omr ; operating mode 0 1103 P:000105 374000 move #$40,r7 ; initialize stack pointer 1104 P:000106 05F427 move #-1,m7 ; linear addressing FFFFFF 1105 P:000108 0BF080 jsr ada_init ; initialize codec 000124 1106 1107 P:00010A 64F400 move #$0400,r4 ; start echo buffer at $400 000400 1108 P:00010C 05F424 move #$03FF,m4 ; make echo buffer 1024 deep 0003FF 1109 1110 P:00010E 200013 clr a ; clear a 1111 P:00010F 06FFA3 rep #$03FF ; clear the echo buffer 1112 P:000110 485C00 move a,l:(r4)+ 1113 1114 echo_loop 1115 Motorola DSP56300 Assembler Version 6.2.0 99-09-08 10:58:29 echo2.asm Page 2 1116 P:000111 01B7A3 jset #3,x:M_SSISR0,* ; wait for rx frame sync 000111 1117 P:000113 01B783 jclr #3,x:M_SSISR0,* ; wait for rx frame sync 000113 1118 P:000115 200013 clr a 1119 P:000116 20001B clr b 1120 P:000117 568000 move x:RX_BUFF_BASE,a ; receive left 1121 P:000118 578100 move x:RX_BUFF_BASE+1,b ; receive right 1122 P:000119 44E422 asr a x:(r4),x0 ; divide them by 2 and get oldest 1123 P:00011A 4EE42A asr b y:(r4),y0 ; samples from buffer 1124 P:00011B 200040 add x0,a ; add the new samples and the old 1125 P:00011C 200058 add y0,b 1126 P:00011D 200022 asr a ; reduce magnitude of new data (to ensure stability) 1127 P:00011E 20002A asr b 1128 P:00011F 566400 move a,x:(r4) ; save the altered samples 1129 P:000120 5F5C00 move b,y:(r4)+ ; and bump the pointer 1130 P:000121 560200 move a,x:TX_BUFF_BASE ; transmit left 1131 P:000122 570300 move b,x:TX_BUFF_BASE+1 ; transmit right 1132 1133 P:000123 0C0111 jmp echo_loop 1134 1135 include 'ada_init.asm' ; used to include codec initialization routines 1136 page 132,60 1137 ;************************************************************************** 1138 ; ADA_INIT.ASM Ver 1.2 1139 ; Example program to initialize the CS4218 1140 ; 1141 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1142 ; Semiconductor Products Sector 1143 ; Wireless Signal Processing Division 1144 ; 1145 ; History: 1146 ; 14 June 1996: RLR/LJD - ver 1.0 1147 ; 21 July 1997: BEA - ver 1.1 1148 ; 23 Sept 1998: TTL - ver 1.2 1149 ;************************************************************************** 1150 X:000006 org x: 1151 1152 ; Codec control constants 1153 X:000006 CTRL_WD_HI ds 1 1154 X:000007 CTRL_WD_LO ds 1 1155 1156 1157 ; GPIO pin constants 1158 1159 ; ESSI0 - audio data GPIO mode 1160 ; DSP CODEC 1161 ; --------------------------- 1162 CODEC_RESET 1163 000000 equ 0 ; bit0 SC00 ---> CODEC_RESET~ 1164 1165 ; ESSI1 - control data GPIO Mode 1166 ; DSP CODEC 1167 ;---------------------------- 1168 000000 CCS equ 0 ; bit0 SC10 ---> CCS~ 1169 000001 CCLK equ 1 ; bit1 SC11 ---> CCLK Motorola DSP56300 Assembler Version 6.2.0 99-09-08 10:58:29 ada_init.asm Page 3 1170 000002 CDIN equ 2 ; bit2 SC12 ---> CDIN 1171 1172 ;************************************************************************** 1173 ; Initialize the CS4218 codec 1174 ; --------------------------- 1175 ; Serial Mode 4 (SM4), DSP Slave/Codec Master, 32-bits per frame 1176 ; 1177 ; After a reset, the control port must be written once to initialize it 1178 ; if the port will be accessed to read or write control bits. The initial 1179 ; write is a "dummy" write since the data is ignored by the codec. A second 1180 ; write is needed to configure the codec as desired. Then, the control port 1181 ; only needs to be written to when a change is desired, or to obtain status 1182 ; information. 1183 ; 1184 ; Although only 23 bits contain useful data in CDIN, a minimum of 31 bits 1185 ; must be written. 1186 ; 1187 ; CDIN 1188 ;------------------------------------------------ 1189 ; bit 31 0 1190 ;------------------------------------------------ 1191 ; bit 30 mask interrupt 1192 ; 0=no mask on MF5:\INT pin 1193 ; 1=mask on MF5:\INT pin 1194 ;------------------------------------------------ 1195 ; bit 29 DO1 1196 ;------------------------------------------------ 1197 ; bits 28-24 left output D/A sttenuation (1.5dB steps) 1198 ; 00000=No attenuation 0dB 1199 ; 11111=Max attenuation -46.5dB 1200 ;------------------------------------------------ 1201 ; bits 23-19 right output D/A attenuation (1.5dB steps) 1202 ; 00000=No attenuation 0dB 1203 ; 11111=Max attenuation -46.5dB 1204 ;------------------------------------------------ 1205 ; bit 18 mute D/A outputs 1206 ; 0=outputs ON 1207 ; 1=outputs MUTED 1208 ;------------------------------------------------ 1209 ; bit 17 input mux, left select 1210 ; 0=RIN1 1211 ; 1=RIN2 (used on EVM) 1212 ;------------------------------------------------ 1213 ; bit 16 input mux, right select 1214 ; 0=LIN1 1215 ; 1=LIN2 (used on EVM) 1216 ;------------------------------------------------ 1217 ; bits 15-12 left input A/D gain (1.5dB steps) 1218 ; 0000=No gain 0dB 1219 ; 1111=Max gain +22.5dB 1220 ;------------------------------------------------ 1221 ; bits 11-8 right input A/D gain (1.5dB steps) 1222 ; 0000=No gain 0dB 1223 ; 1111=Max gain +22.5dB 1224 ;------------------------------------------------ 1225 ; bits 7-0 00000000 Motorola DSP56300 Assembler Version 6.2.0 99-09-08 10:58:29 ada_init.asm Page 4 1226 ;------------------------------------------------ 1227 ;************************************************************************** 1228 1229 1230 P:000124 org p: 1231 ada_init 1232 1233 ; reset ESSI ports 1234 P:000124 07F43F movep #$0000,x:M_PCRC ; reset ESSI0 port 000000 1235 P:000126 07F42F movep #$0000,x:M_PCRD ; reset ESSI1 port 000000 1236 1237 ; Set Control Register A and B 1238 P:000128 07F435 movep #$101807,x:M_CRA0 ; 12.288MHz/16 = 768KHz SCLK 101807 1239 ; prescale modulus = 8 1240 ; frame rate divider = 2 1241 ; 16-bits per word 1242 ; 32-bits per frame 1243 ; 16-bit data aligned to bit 23 1244 1245 P:00012A 07F436 movep #$ff330c,x:M_CRB0 ; Enable REIE,TEIE,RLIE,TLIE, FF330C 1246 ; RIE,TIE,RE,TE0 1247 ; network mode, synchronous, 1248 ; out on rising/in on falling 1249 ; shift MSB first 1250 ; external clock source drives SCK 1251 ; (codec is master) 1252 ; RX frame sync pulses active for 1253 ; 1 bit clock immediately before 1254 ; transfer period 1255 ; positive frame sync polarity 1256 ; frame sync length is 1-bit 1257 1258 ; Configure GPIO pins -- (functionality and direction ) 1259 P:00012C 07F43F movep #$0000,x:M_PCRC ; Enable GPIO pin 0 SC00=CODEC_RESET 000000 1260 P:00012E 07F42F movep #$0000,x:M_PCRD ; Enable GPIO CSS (pin 0),CCLK (pin 1), CDIN (pin 2) 000000 1261 1262 P:000130 07F43E movep #$0001,x:M_PRRC ; set PC0=CODEC_RESET~ as output 000001 1263 P:000132 07F42E movep #$0007,x:M_PRRD ; set PD0=CCS~ as output 000007 1264 ; set PD1=CCLK as output 1265 ; set PD2=CDIN as output 1266 1267 ; Codec Reset 1268 P:000134 013D00 bclr #CODEC_RESET,x:M_PDRC ; assert CODEC_RESET~ 1269 P:000135 012D00 bclr #CCS,x:M_PDRD ; assert CCS~ -- allows control register to be writte n to 1270 1271 ; Delay to allow Codec to reset Motorola DSP56300 Assembler Version 6.2.0 99-09-08 10:58:29 ada_init.asm Page 5 1272 P:000136 06E883 do #1000,_delay_loop 000139 1273 P:000138 06E8A3 rep #1000 ; minimum 50 ms delay 1274 P:000139 000000 nop 1275 _delay_loop 1276 1277 1278 ; Setting up to send Codec control information 1279 P:00013A 013D20 bset #CODEC_RESET,x:M_PDRC ; deassert CODEC_RESET~ 1280 1281 1282 ; Sending control words 1283 set_control 1284 P:00013B 44F400 move #CTRL_WD_12,x0 ; transfer control value to control variable 000300 1285 P:00013D 440600 move x0,x:CTRL_WD_HI 1286 P:00013E 240000 move #CTRL_WD_34,x0 1287 P:00013F 440700 move x0,x:CTRL_WD_LO 1288 P:000140 0BF080 jsr codec_control ; send in dummy control information 00014A 1289 P:000142 0BF080 jsr codec_control ; send in correct control information 00014A 1290 1291 1292 ; Set and enable interrupts 1293 P:000144 08F4BE movep #$000c,x:M_IPRP ; set interrupt priority level for ESSI0 to 3 00000C 1294 P:000146 00FCB8 andi #$fc,mr ; enable interrupts 1295 1296 ; Set ESSI functionality 1297 P:000147 07F43F movep #$003e,x:M_PCRC ; enable ESSI0 except SC00=CODEC_RESET 00003E 1298 1299 P:000149 00000C rts 1300 1301 1302 ;------------------------------------------------------------- 1303 ; codec_control routine 1304 ; Input: CTRL_WD_LO and CTRL_WD_HI 1305 ; Output: CDIN 1306 ; Description: Used to send control information to CODEC 1307 ; NOTE: does not preserve the 'a' register. 1308 ;------------------------------------------------------------- 1309 codec_control 1310 P:00014A 200013 clr a 1311 P:00014B 012D00 bclr #CCS,x:M_PDRD ; assert CCS 1312 P:00014C 548600 move x:CTRL_WD_HI,a1 ; upper 16 bits of control data 1313 P:00014D 0BF080 jsr send_codec ; shift out upper control word 000154 1314 P:00014F 548700 move x:CTRL_WD_LO,a1 ; lower 16 bits of control data 1315 P:000150 0BF080 jsr send_codec ; shift out lower control word 000154 1316 P:000152 012D20 bset #CCS,x:M_PDRD ; deassert CCS 1317 P:000153 00000C rts 1318 1319 Motorola DSP56300 Assembler Version 6.2.0 99-09-08 10:58:29 ada_init.asm Page 6 1320 ;--------------------------------------------------------------- 1321 ; send_codec routine 1322 ; Input: a1 containing control information 1323 ; Output: sends bits to CDIN 1324 ; Description: Determines bits to send to CDIN 1325 ;--------------------------------------------------------------- 1326 1327 send_codec 1328 P:000154 061080 do #16,end_send_codec ; 16 bits per word 000160 1329 P:000156 012D21 bset #CCLK,x:M_PDRD ; toggle CCLK clock high 1330 P:000157 0ACC17 jclr #23,a1,bit_low ; test msb 00015C 1331 P:000159 012D22 bset #CDIN,x:M_PDRD ; send high into CDIN 1332 P:00015A 0AF080 jmp continue 00015D 1333 bit_low 1334 P:00015C 012D02 bclr #CDIN,x:M_PDRD ; send low into CDIN 1335 continue 1336 P:00015D 0602A0 rep #2 ; delay 1337 P:00015E 000000 nop 1338 P:00015F 012D01 bclr #CCLK,x:M_PDRD ; restart cycle 1339 P:000160 200033 lsl a ; shift control word to 1 bit 1340 ; to left 1341 end_send_codec 1342 P:000161 00000C rts 1343 1344 1345 1346 1347 ;**************************************************************************** 1348 ; SSI0_ISR.ASM Ver.2.0 1349 ; Example program to handle interrupts through 1350 ; the 56307 SSI0 to move audio through the CS4218 1351 ; 1352 ; Copyright (c) MOTOROLA 1995, 1996, 1997, 1998 1353 ; Semiconductor Products Sector 1354 ; Digital Signal Processing Division 1355 ; 1356 ; 1357 ; History: 1358 ; 14 June 1996: RLR/LJD - ver 1.0 1359 ; 23 July 1997: BEA - ver 1.1 1360 ;****************************************************************************** 1361 1362 1363 ;----the actual interrupt service routines (ISRs) follow: 1364 1365 ;************************ SSI TRANSMIT ISR ********************************* 1366 ssi_txe_isr 1367 P:000162 013704 bclr #4,x:M_SSISR0 ; Read SSISR to clear exception flag 1368 ; explicitly clears underrun flag 1369 ssi_tx_isr 1370 P:000163 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1371 P:000164 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1372 P:000165 0501A0 move #1,m0 ; Modulus 2 buffer. Motorola DSP56300 Assembler Version 6.2.0 99-09-08 10:58:29 ada_init.asm Page 7 1373 P:000166 608500 move x:TX_PTR,r0 ; Load the pointer to the tx buffer. 1374 P:000167 000000 nop 1375 P:000168 000000 nop 1376 P:000169 000000 nop 1377 P:00016A 07D83C movep x:(r0)+,x:M_TX00 ; SSI transfer data register. 1378 P:00016B 600500 move r0,x:TX_PTR ; Update tx buffer pointer. 1379 P:00016C 05FF20 move x:-(r7),m0 ; Restore m0. 1380 P:00016D 60FF00 move x:-(r7),r0 ; Restore r0. 1381 P:00016E 000004 rti 1382 1383 ;********************* SSI TRANSMIT LAST SLOT ISR ************************** 1384 ssi_txls_isr 1385 P:00016F 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1386 P:000170 300200 move #TX_BUFF_BASE,r0 ; Reset pointer. 1387 P:000171 000000 nop 1388 P:000172 600500 move r0,x:TX_PTR ; Reset tx buffer pointer just in 1389 P:000173 000000 nop ; case it was corrupted. 1390 P:000174 60FF00 move x:-(r7),r0 ; Restore r0. 1391 P:000175 000004 rti 1392 1393 ;************************** SSI receive ISR ******************************** 1394 ssi_rxe_isr 1395 P:000176 013705 bclr #5,x:M_SSISR0 ; Read SSISR to clear exception flag 1396 ; explicitly clears overrun flag 1397 ssi_rx_isr 1398 P:000177 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1399 P:000178 055F20 move m0,x:(r7)+ ; Save m0 to the stack. 1400 P:000179 0501A0 move #1,m0 ; Modulus 2 buffer. 1401 P:00017A 608400 move x:RX_PTR,r0 ; Load the pointer to the rx buffer. 1402 P:00017B 000000 nop 1403 P:00017C 000000 nop 1404 P:00017D 000000 nop 1405 P:00017E 075838 movep x:M_RX0,x:(r0)+ ; Read out received data to buffer. 1406 P:00017F 600400 move r0,x:RX_PTR ; Update rx buffer pointer. 1407 P:000180 05FF20 move x:-(r7),m0 ; Restore m0. 1408 P:000181 60FF00 move x:-(r7),r0 ; Restore r0. 1409 P:000182 000004 rti 1410 1411 ;********************** SSI receive last slot ISR ************************** 1412 ssi_rxls_isr 1413 P:000183 605F00 move r0,x:(r7)+ ; Save r0 to the stack. 1414 P:000184 300000 move #RX_BUFF_BASE,r0 ; Reset rx buffer pointer just in 1415 ; case it was corrupted. 1416 P:000185 600400 move r0,x:RX_PTR ; Update rx buffer pointer. 1417 P:000186 60FF00 move x:-(r7),r0 ; Restore r0. 1418 P:000187 000004 rti 1419 echo 1420 end 0 Errors 0 Warnings